An FPGA Implementation of a transparent bridge between a CPU and a SPI Flash memory interface, through a FIFO.
The interface includes several communicating statemachines to handle command- and data transfer protocols between the host and the Flash.
An FPGA Implementation of a transparent bridge between a CPU and a SPI Flash memory interface, through a FIFO.
The interface includes several communicating statemachines to handle command- and data transfer protocols between the host and the Flash.
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